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Release Candidate Firmware V1.20 RC5
#88
I noticed the clock multiplication and division being buggy
I'm using version 1.20 RC3 with a saved file from 1.19
using the FX 1 SCLK 009 regular clock if I change that to SCLK 008
before the loop finishes it takes 2 loops before changing to the new division
on a 16step loop using
BRK 000 on step 07
Live Quantize is set to 8 steps
seems to work fine with odd divisions goin from a multiply 3 to 5 and back
I think it's happening only when goin from regular clock to another division or multiplication
my issue is I have pattern that has division /32
goin to a pattern that has a regular clock
it changes to the new pattern but does not change the clock time
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Messages In This Thread
RE: Release Candidate Firmware V1.20 RC3 - by Mat - 08-27-2019, 10:47 AM
RE: Release Candidate Firmware V1.20 RC3 - by Mat - 09-03-2019, 10:56 AM
RE: Release Candidate Firmware V1.20 RC3 - by castano - 09-27-2019, 04:37 PM
RE: Firmware V1.20 Release Candidate - by ehr - 07-26-2019, 04:01 PM
RE: Firmware V1.20 Release Candidate - by modbang - 07-26-2019, 07:38 PM
RE: Firmware V1.20 Release Candidate - by skybox - 07-26-2019, 07:50 PM
Lockup loading proj. with 1.20 RC - by StateAzure - 08-05-2019, 04:39 PM

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